The present invention relates generally to the field of junction field-effect transistors (JFETs), and more particularly to structures for thin-film JFETs.
Hydrogenated amorphous silicon (a-Si:H) enjoys widespread use in the production of thin-film transistors (TFTs), image sensors, photo-receptors and solar cells. This material is typically grown by plasma-enhanced chemical vapor deposition (PECVD) at temperatures close to 200° C., suitable for low-cost, large-area substrates. Low-cost, large-area processing is highly desirable for applications in large-area electronics, such as the fabrication of TFT backplanes for active-matrix displays.
However, applications requiring large and stable drive currents such as high-resolution active-matrix organic light-emitting diode displays pose some challenges to the use of a-Si:H TFTs. Large-area deposition techniques are typically suited for growing non-crystalline materials, but devices constructed from these materials suffer from inferior performance relative to those made from crystalline materials. At the same time, processing single-crystalline devices typically requires a complementary metal-oxide-semiconductor (CMOS) foundry, which is too expensive for large-area electronics and displays.
With the advent of various layer-transfer techniques to enable the transfer of thin layers of crystalline silicon (c-Si) onto low-cost substrates such as glass or plastic, thin-film heterojunction field-effect transistor (HJFET) devices with c-Si channels and PECVD contact regions are known.